1. Field of the Invention
The present invention generally relates to circuit testing and, more particularly, to a method and means for testing and analysing the performance of electronic circuitry of different integration sizes and types.
2. Description of the Prior Art
In the production and use of circuits of the same design, hereafter referred to as identical circuits, which may be electrical, digital or analog or different integration sizes and either in dynamic or static states, testing of every or most of the produced circuits is either required or highly desirable. To this end various automatic test equipment (ATE) have been developed. An ATE typically includes a source of electrical stimuli, e.g. a source of input signals, which are applied to each circuit to be tested, hereafter referred to by the acronym UUT, for unit under test. Also included in the ATE are devices which measure the output signals from the UUT, as well as some signals at junction points or nodes of the UUT. A computer, either a special purpose computer or a properly programmed general purpose computer is also included. The measured signals are fed to the computer, wherein various information, pertaining to input-output ratios and allowed tolerances are stored. The computer, by means of its processor unit, controls the stimulation and measurements' sequences, as well as, other sequences, to determine whether or not the UUT operates satisfactorily and the location of malfunctions, if any.
Before testing the various identical circuits of a set of circuits, an extensive study or analysis of the basic circuit must take place. The analysis involves predicting expected circuit outputs for specified inputs, and an analysis of unexpected outputs at the circuit's output terminals and at intermediate nodes, as a result of one or more faulty components. Such analysis, which is time consuming, may dictate the testing of the circuit by applying additional inputs and measuring additional outputs.
Such an ATE is quite expensive. Also, the testing of each UUT is quite time consuming, particularly when the circuit is of any level of complexity and includes a reasonably large number of nodes. A need therefore exists for a new method and means for expediting and simplifying the testing of circuits.